1. Field of the Invention
The invention relates to computer systems and, more particularly, to computer systems having multiple processors interconnected by a pended bus.
2. Description of the Related Art
Modern computer systems may have multiple processors, memory resources, and input/output (I/O) devices interconnected by a common bus to achieve high total computational power. Such construction can provide very powerful systems capable of executing many millions of instructions per second. However, the interconnection of multiple processors can create difficulties when there is a need to perform an instruction sequence known as a read-modify-write (RMW) operation. In an RMW operation, one processor retrieves data from a memory location, performs an operation on the data, and writes the modified data back to the original memory location. Unpredictable results affecting data integrity can occur if one processor has started an RMW operation for one memory location, and a second processor attempts an RMW operation for the same memory location in the time period between the "read" operation of the first processor's RMW operation and the "write" portion of that RMW operation.
One way to prevent multiple processors from performing RMW operations on the same memory locations is to provide an exclusive RMW operation using an "interlock read" capability. This involves the use of a "lock" indicator, such as a lock bit, which is set when the "read" portion of an RMW operation is performed and which is reset after the "write" portion of the RMW operation is completed. A second processor attempting to initiate an RMW operation on a location in memory when the lock bit is set will cause the memory to return lock status information by means of a "busy" or "retry" confirmation a predetermined number of bus cycles after the second processor generated its interlock read command. The busy confirmation indicates to the processor that the second interlock read command was not accepted by the memory
The interlock read operation alleviates problems caused by multiple processors each attempting to perform an RMW operation. Processors are granted equitable access to the bus for such interlock read operations by arbitration processes using, for example, a round-robin algorithm. However, performance bottlenecks can still occur. For example, under certain bus traffic conditions, a specific processor may repeatedly encounter locked memory locations and will be unable to obtain needed access to memory resources in a timely manner. Such problems could be reduced by providing multiple lock bits for a memory node with each lock bit associated with a portion of the memory node rather than with the whole memory node. Such multiple lock bits would provide finer "granularity" of interlocked read operations on a memory node, tying up a smaller portion of memory after an interlock read operation. This solution would also permit a higher success rate of RMW operations, thus improving system throughput. However, implementing multiple lock bits on prior art pended bus multiprocessor systems would result in unacceptably complex circuitry for detecting and transmitting lock status information.
Although the preceding discussion has emphasized the operation of a computer system employing processor nodes, memory nodes, and I/O nodes, a more general discussion of such a system is in the terms of commander nodes, that is, nodes which initiate a transaction on a bus, and responder nodes, that is, nodes which respond to a transaction initiated by a commander node. At various times, a single device can function as either a commander node or a responder node.
It is desirable to provide a computer system in which devices are interconnected over several busses, each having different characteristics. However, this was extremely difficult to accomplish in prior art pended bus systems using interlock read operations, in which lock status information was transmitted with a fixed time relationship to the initial interlocked read command.